Radio frequency (RF) transmitters of the type used in mobile wireless telephones (also known as cellular telephones) and other portable radio transceivers commonly include transmit power control circuitry that adjusts the power of the transmitted RF signal. The power control circuitry can adjust a power amplifier to increase or decrease the transmitted RF power. Adjusting transmitted RF power is useful for several purposes. For example, in many types of cellular telecommunications systems, it is useful for transmitted RF power to be higher when the transceiver (also referred to as a handset) is farther from the nearest base station and lower when the transceiver is closer to the nearest base station. Also, in some types of multi-mode (e.g., dual-mode) transceivers, such as those that are capable of operating in accordance with both the GSM (Global System for Mobile telecommunication) standard and EDGE (Enhanced Data rates for GSM Evolution) standard, requirements for transmitted RF power differ depending on whether the transceiver is operating in GSM mode or EDGE mode. Similarly, requirements for transmitted RF power can differ in multi-band (e.g., dual-band) transceivers, such as those that are capable of operating in both a GSM “low band” frequency band (e.g., the 880-915 MHz frequency band that is used in much of Europe, Africa, the Middle East and Asia) and a GSM “high band” frequency band (e.g., the 1850-1910 MHz frequency band that is used in the United States). To accommodate different power amplification requirements for multiple bands, the power amplifier system of the transceiver may correspondingly include multiple power amplifiers.
In some applications, the power amplifier system of a portable radio transceiver includes a negative feedback power control loop to adjust the output power of the power amplifier to a level within the tolerance range specified by the mode under which the transceiver is operating. For example, while a transceiver is transmitting in GSM mode, the power control loop strives to maintain the amplifier output power within the tolerance range specified by the GSM standard for the frequency-shift keying-modulated (specifically, Gaussian Minimum Shift Keying (GMSK)) signal that is transmitted in accordance with the GSM standard. Likewise, while the transceiver is transmitting in EDGE mode, the control loop strives to maintain the amplifier output power within the tolerance range specified by the EDGE standard for the 8-phase-shift keying (8PSK)-modulated signal that is transmitted in accordance with the EDGE standard. In general, the feedback loop compares a feedback quantity, such as detected RF output power level, with a reference control voltage. The difference between the two voltages (also referred to as difference error) is integrated and applied to the power control port of the power amplifier. For GMSK, the power amplifier power control port is typically a voltage controlled input (V_PC), which adjusts the power amplifier bias. The RF input level is fixed. For EDGE, the power amplifier power control port is the RF input level. In EDGE, V_PC can also be adjusted to optimize efficiency while maintaining linearity. The large loop gain minimizes the difference error and drives the output power accuracy to the precision of the loop feedback circuitry and reference control voltage.
A power amplifier control loop can undesirably voltage-saturate under conditions such as insufficient battery power and VSWR (voltage standing wave ratio) load line extremes. Such conditions can cause an undesirable decrease in control loop gain, increase in difference error, or both. These effects can manifest themselves in sluggish control loop response, resulting in drifting power amplifier output power level or even complete loss of control loop lock.
Power control loop saturation can also result in switching spectrum degradation and nonconformance with applicable transmission standards (e.g., GMSK), such as exceeding power-versus-time (PvT) measurements specified by the applicable standard. Furthermore, peaks of an amplitude-modulated EDGE signal envelope can become clipped, causing modulation spectrum degradation.
To avoid power control loop saturation, some power amplifier systems have included circuitry that monitors the loop error voltage and reduces the loop reference voltage until the loop error is eliminated. Alternatively, a power amplifier system can include saturation detection circuitry that detects when the control loop is nearing saturation and activates a “saturation detect” signal. The power control circuitry responds to this signal by reducing the target output power until the saturation detection circuitry deactivates the “saturation detect” signal, indicating normal or non-saturated control loop operation.
For example, as illustrated in FIG. 1, the gain, or amplification, of a power amplifier 10 is controlled by a voltage regulator 12 comprising an operational amplifier 13, a PFET (p-channel field-effect transistor) 14, and associated resistors 16 and 18. Power amplifier 10 can include a number of cascaded stages, but only the transistor 20 of the final stage is shown for purposes of clarity (other such stages being indicated by the ellipsis (“ . . . ”) symbol). Voltage regulator 12 is responsive to a power control signal (V_PC) that is produced by power control circuitry (not shown for purposes of clarity). Note that the output of operational amplifier 13 is coupled via PFET 14 to the collector terminal of transistor 20. Such an arrangement provides what is known as collector voltage amplifier control (COVAC).
The circuitry for generating a “saturation detect” signal includes a comparator 22, a current source 24, and a resistor 26. A power supply voltage (V_BATT) provided by a battery-operated power supply (not shown for purposes of clarity) is coupled to the source terminal of PFET 14 and one terminal of resistor 26. A power supply-dependent reference voltage is applied to one terminal of comparator 22 via resistor 26 and current source 24. The other terminal of comparator 22 receives the drain voltage of PFET 14. If the PFET 14 drain voltage exceeds the comparator reference voltage, comparator 22 generates a “saturation detect” signal indicating that the voltage regulator is saturated. The regulator gain-bandwidth is insufficient to accurately follow the V_PC input signal, resulting in power amplifier PvT time mask and switching spectrum specification violations.
While the technique described above with reference to FIG. 1 for detecting when a power amplifier control loop is in or near saturation is useful in a power amplifier system having a COVAC transistor arrangement, the technique cannot be used in some other cases. For example, in some power amplifier transistor arrangements, the collector of the final-stage transistor is directly connected to the power supply voltage (V_BATT).